FIG. 1 shows a conventional fractional-n digital phase lock loop (PLL) circuit 100. The circuit includes a phase frequency detector (PFD) 101. The PFD 101 has two inputs. A first input 102 carries a reference signal. The reference signal is typically obtained from an incoming radio signal. A second input 103 originates from voltage controlled oscillator (VCO) 104. The output of the voltage controlled oscillator 104 is passed through divide by n counter 105. The output of the divide by n counter 105 is connected to the second input 103 of the PFD 101. The voltage control oscillator 104 and the divide by n counter 105 are set such that the signal arriving at the second input 103 is approximately the same frequency as the reference signal present at the first input 102.
The PFD 101 monitors the signals arriving at its two inputs. It is arranged to provide different outputs depending on the phase and frequency differences between the two input signals. If a wave front of the reference signal arriving at input 102 leads a wave front of the signal arriving at the second input 103, the PFD 101 outputs pulses via up output 106. The so-called UP signal varies in length depending on how much the two signals are out of phase. If a wave front of the signal arriving at the second input 103 leads a wave front of the reference signal arriving at the first input 102, then the PFD 101 outputs pulses at down output 107. The so-called DOWN signal varies in length depending on how much the two signals are out of phase. The circuit 100 also includes a charge pump 108. The charge pump has two inputs, one connected to up output 106, and one connected to down output 107. The charge pump includes current generators which are arranged to drive current towards output 109 or source current away from output 109. If the charge pump receives an UP signal, the charge pump drives current towards output 109. If the charge pump receives a DOWN signal, the charge pump sources current away from output 109.
The circuit also includes a low pass filter 110 which is connected to the charge pump via output 109. The low pass filter smoothes any signals being outputted by the charge pump 108. The low pass filter is connected to the VCO 104. When the PFD 101 produces an UP signal, the frequency of the signal being produced by the VCO 104 will increase. Thus, the signal arriving at the second input 103 will catch up with the reference signal. When the PFD 101 produces a DOWN signal, the frequency of the signal being produced by the VCO 104 will decrease. Thus, the signal arriving at the reference signal will catch up with the signal arriving at the second input 103.
In the above-described manner, the circuit produces a sinusoidal output signal at output 111 which is at the frequency of the reference signal, divided by N.
In order for a PLL circuit, such as circuit 100, to produce a pure sinusoidal output, the PFD 101, and hence the charge pump 108, needs to produce a linear output. A typical phase frequency detector includes a sigma delta modulator. Sigma delta modulators produce out-of-band phase errors. Any non-linearity in the PFD 101 will be folded into the PLL bandwidth. This creates in-band noise and spurs.
FIG. 2 is a graph of phase noise after the charge pump at an RF divider input after a divide by two in a PLL circuit known from the prior art. The x-axis is frequency in Hertz. The y-axis shows phase noise per Hertz in dBc/Hz units. As can be seen, the graph shows a non-linear phase detector and a linear, or ideal phase detector.
There are two known types of non-linearity in PFD circuits. These are integral non-linearity and differential non-linearity. FIGS. 3 and 4 are graphs showing differential non-linearity at the output of the charge pump which is caused by non-linearity in the PFD. FIG. 3 shows charge pump characteristics and phase error distribution. The x-axis is phase (ns) and the y-axis is normalized charge pump output charge every period. FIG. 4 shows the derivative of the charge pump characteristics. The x-axis is phase (ns) and the y-axis is the derivative of normalized charge pump output charge every period.
Differential non-linearity is not particularly well understood and there has been little or no identification or study of the causes of differential non-linearity in the available technical literature.
There is therefore a need for identification of causes for non-linearity and also for improved circuits designed to reduce non-linearity.